1. Field of the Invention
The present invention relates to an LSI (integrated circuit) design method, and more particularly to a design method for an integrated circuit equipped with a scan function.
2. Description of the Related Art
LSI design steps include a logic design step of designing a logic circuit for implementing a desired function; a step of laying out logic macros and logic cells that constitute the logic circuit, and interconnects connecting these logic cells on the basis of a netlist generated in the logic design step, and a verification step of performing timing verification for the logic circuit thus laid out, and so forth. In order to lay out the logic macros and logic cells and so forth, reference is made to a layout library containing the corresponding layout data. Further, the test patterns which are used in the timing verification are obtained by referencing a logic library that comprises function data for the logic macros and logic cells and so forth.
Logic cells are relatively small-scale circuit units such as flip flops, and NAND and NOR gates and the like, and logic macros are relatively large-scale circuit units such as processors and the like. However, both logic cells and logic macros are circuit units having predetermined functions and are registered in the logic library and the layout library, and are therefore referred to below generically as ‘standard cells’ or ‘cells’.
In enlarged-scale LSIs, a scan circuit constituting a verification circuit is generally provided. In other words, in the design step, a plurality of flip flops in the logic circuit are substituted for flip flops equipped with a scan function and a circuit constitution in which these flip flops are connected by scan chain interconnects is produced. In the verification step, predetermined test data are inputted to the plurality of flip flops by being scanned in and, after the logic circuit has been caused to perform a predetermined cycle operation, the data in these flip flops are outputted by being scanned out, and a process of verifying whether or not the outputted data match the expected values is performed. The test data are generated automatically by means of a computer design tool on the basis of a circuit which includes the logic-designed logic circuit and the added scan circuit. Further, as described earlier, in order to generate the test data, reference is made to a logic library containing logic data for the cells that constitute the logic circuit.
FIG. 1 is a flowchart showing conventional LSI design steps. Steps S1 to S4 of FIG. 1 are all performed by means of functions which the CAD design tool comprises. First, at the point when the logic design step S1 is complete, a netlist NL1 containing data for connections between the cells that constitute the logic circuit is generated. At this stage, the netlist NL1 does not contain a verification scan circuit, that is, does not contain test data (DFT: Design For Test).
Therefore, in a test circuit synthesis step S2, delay flip flops (D-FF) in the logic circuit are extracted and then substituted for scan flip flops equipped with a scan function, and a scan chain is formed by connecting these scan flip flops in an arbitrary order. As a result, a netlist NL2 is generated. This netlist NL2 is data in which delay flip flops of the netlist NL1 generated in the logic design step S1 are substituted for scan flip flops, and includes connection data for forming the scan chain in addition to the connection data of the netlist NL1.
Test patterns are automatically generated (S3) for the logic circuit equipped with the scan circuit which is contained in the netlist NL2. In the step of automatically generating the test patterns, reference is made to a logic library F10 that contains data for the logic circuit equipped with the scan circuit which is contained in the netlist NL2, and logic data for the cells that constitute the logic circuit and for the added scan flip flops, whereby an input test pattern and the expected output test pattern are generated. These test patterns are registered in the form of a test pattern file F12 and used in the subsequent timing verification step (not shown).
In addition, an automatic layout & wiring step S4 is performed on the basis of the netlist NL2. In the automatic layout & wiring step S4, the layout of the cells in the netlist NL2 that constitute the logic circuit and the layout of interconnects that connect these cells are performed with reference to a layout library F14. As a result, a layout data file F16 is generated for the netlist NL2. This layout data file also contains layout data for the scan flip flops and the scan interconnects that connect the scan flip flops to constitute the scan chain. For this reason, reference is made in the automatic layout & wiring step S4 to the layout library F14 for a scan flip flop in addition to the layout library F14 for the cells constituting the logic circuit.
Here, the test data DFT represents scan flip flops and interconnects that connect same. According to conventional methods, the test data contained in the netlist NL2 is constituted by scan flip flops which are hard macros. ‘Hard macros’ refer to cells that are registered in the layout library and that can be laid out directly from a netlist. Therefore, in the above-cited example, the scan flip flops are hard macros because same are registered in the layout library. On the other hand, ‘soft macros’ are not registered in the layout library. Therefore, in order to be laid out, the soft macros are each developed as a plurality of hard macros (standard cells) which implement the functions of the soft macro, it being necessary to use the layout data of the layout library for these developed standard cells.
Returning now to FIG. 1, a check is also performed, for the layout data F16 generated in the automatic layout and wiring step S4, of whether or not all of the interconnects thus laid out can be realized. When the interconnects cannot be implemented, a check is made of whether or not the interconnects for the scan chain of the scan circuit can be laid out when priority is given to the cells that constitute the logic circuit and to the interconnects connecting these cells. When this is not possible, a re-order step is performed in which the order of the scan chain wiring alone is changed without changing the disposition of the cells and the interconnects connecting same. This is because, by changing the order of the scan chain, the interconnects connecting same are simplified and there is the probability that the layout will then be feasible. Because the scan circuit will change if the re-order step is carried out, the test pattern automatic generation step S3 is repeated such that the test patterns F12 are re-created for the logic circuit having the new scan chain.
However, as mentioned earlier, in order to generate the layout data from the netlist in accordance with the automatic layout and wiring step, reference must be made to the hard macros that contain the layout information for the standard cells registered in the layout library. Hence, in addition to the hard macros of the standard cells contained in the netlist NL1 that is generated in the logic design step S1, the hard macros of the scan flip flops introduced in the test circuit synthesis step S2 must also be registered in the layout library F14.
Therefore, in order to design a logic circuit with a scan function and perform the layout thereof, a layout library (hard macro library) for the scan flip flops serving to implement the scan function is required, and there are therefore problems such as an increase in the man hours involved in the library registration.
Further, in a case where a scan circuit for implementing the scan function is introduced and this circuit is developed as a plurality of standard cells without the use of a scan flip flop layout library, there are problems such as an increase in circuit scale.